The present invention relates generally to a true type single-phase shift circuit and more particularly to a single-phase shift circuit that enhances the adaptability of a circuit to an incoming clock pulse whose rise and fall time may not perfectly match the strict requirements of a conventional single-phase shift circuit, and whose schematic circuit layout is more concise in design.
FIG. 1 is a schematic circuit diagram of a prior art CMOS true type single-phase shift circuit published in the IEEE Journal of Solid-Circuits, Feb. 1989, by Jiren Yuan and Christer Svensson; wherein, FIG. 1(a) is a schematic circuit diagram of a true single-phase, positive-edge-triggered shift circuit (tspps) 1 and FIG. 1(b) is a schematic circuit diagram of a true single-phase, negative-edge-triggered shift circuit (TSPPS) 2. The prior art CMOS true single-phase shift circuits, 1 and 2, are cascaded in three sections, a first section 12, a second section 14, and a third section 16, each section including three MOS transistors.
Shift circuit 1 includes PMOS transistor 122, 142, 162, and 124; and NMOS transistors 126, 146, 166, 144, and 164. The gates of PMOS transistor 122 and the gate of NMOS transistor 126 are connected to a data signal D; the gates of PMOS transistors 124, 142 and the gates of NMOS transistors 146, 164 are connected to the clock pulse signal C; and the drains of PMOS transistor 162 and the drain of NMOS transistor 164 are coupled to output terminal Q.
Shift circuit 2 is similar to shift circuit 1 except that PMOS 124, NMOS 144, and NMOS 164 are replaced by NMOS 224, PMOS 244, and PMOS 264; and the output terminal Q of shift circuit 2 is coupled to PMOS 264 and NMOS 166. In order to simplify the denotation, all the remaining transistors in FIG. 1(a) and 1(b) are labelled with corresponding numbers.
In the prior art shifters, second section 14 normally performs pre-charge or pre-discharge. Consequently, the rise and fall time of a clock pulse is critical to the proper functioning of the prior art shifters. For example, as seen in Table 1, a shift register using the shifters of the prior art (as in FIG. 4) cannot function properly if the rise and fall time of its clock pulse is longer than 0.8 ns. This restriction on the clock pulse not only limits the usefulness of prior art shifters 1, 2, but also complicates the circuit design.